HOME / p10-embed / [p10-tutorial]
![]() | HARVARD ARCHITECTUREPrinter Friendly Version: click on title |
Your browser doesn't seem to have Javascript support.
Some pages may require Javascript & CSS2 to work properly.

The term originated from the Harvard Mark 1 relay-based computer, which stored instructions on punched tape and data in relay latches.
Harvard Architecture: The Harvard architecture uses physically separate memories for their instructions and data, requiring dedicated buses for each of them. Instructions and operands can therefore be fetched simultaneously.
Different program and data bus widths are possible, allowing program and data memory to be better optimized to the architectural requirements. E.g.: If the instruction format requires 14 bits then program bus and memory can be made 14-bit wide, while the data bus and data memory remain 8-bit wide.
| All trademarks used on these web pages are properties of their respective owners. | |
|
This information is provided in the hope that it will be useful,
but without any warranty, implied or otherwise. We disclaim any liability for
the material published here.
We are not responsible for the contents of web pages referenced by this site. Please send corrections to: p DOT hof AT elec.canterbury.ac.nz. No emails will be answered. Thanks! | |
| Copyright© Philipp Hof. All Rights Reserved. | |
| http://www.elec.canterbury.ac.nz/publicarea/staff/hof | |