HOME / p10-embed / [p10-tutorial]

Big Head

HARVARD ARCHITECTURE

Printer Friendly Version: click on title

Head 1Head 2Head 3
HOME | UP | [...] | << | >>

Your browser doesn't seem to have Javascript support.
Some pages may require Javascript & CSS2 to work properly.

Harvard Architecture

The term originated from the Harvard Mark 1 relay-based computer, which stored instructions on punched tape and data in relay latches.

Harvard Architecture: The Harvard architecture uses physically separate memories for their instructions and data, requiring dedicated buses for each of them. Instructions and operands can therefore be fetched simultaneously.

Different program and data bus widths are possible, allowing program and data memory to be better optimized to the architectural requirements. E.g.: If the instruction format requires 14 bits then program bus and memory can be made 14-bit wide, while the data bus and data memory remain 8-bit wide.